This application claims the priority of Korean Patent Application No. 2003-58253, filed on Aug. 22, 2003, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a program voltage generation circuit for stably programming a flash memory cell and a method of programming a flash memory cell.
2. Description of the Related Art
As flash memory is used in, for example, portable products and built-in products both having increased storage capacities. The demand for flash memory is sharply increasing. Flash memory can replace large storage media such as a hard disk and is used in, for example, digital cameras, voice mail systems, and the like. Compared with nonvolatile memory devices that can perform electrical programming and erasure, NOR flash memory devices perform exceedingly fast programming and reading, so that they are very popular to users who want a fast operation.
FIG. 1 is a schematic diagram of a flash memory cell. Referring to FIG. 1, the flash memory cell has a structure in which a floating gate and a control gate are formed over a channel region between a source and a drain. The flash memory cell is programmed using a Channel Hot Electron Injection (CHEI) method, where channel hot electrons are formed on the side of the drain and injected into the floating gate. Also, the flash memory cell performs erasure by erasing the electrons stored in the floating gate using a Fowler-Nordheim tunneling technique.
FIG. 2 is a circuit diagram of a core cell array of a NOR flash memory. Referring to FIG. 2, zeroth through j-th word lines are arrayed in rows, and zeroth through i-th bit lines are arrayed in columns, thereby forming a matrix. In this matrix, flash memory cells as shown in FIG. 1 are formed at intersection points between the zeroth through j-th word lines and the zeroth through i-th bit lines. Word line voltages Vwl(j) are applied to control gates of the flash memory cells, source voltages Vs(k) are applied to sources thereof, and bit line voltages Vbl(i) are applied to drains thereof.
Reading, programming, and erasure of flash memory cells are performed using operating voltages shown in FIG. 3. Referring to FIG. 3, the flash memory cells are read out using a word line voltage Vwl of about 1.5V, a source voltage Vs of 0V, and a bit line voltage Vbl of about 0.7V. The flash memory cells are programmed using a word line voltage Vwl of about 1.4V, a source voltage Vs of about 8V, and a bit line voltage Vbl of about 0.4V. The flash memory cells are erased using a word line voltage Vwl of about 11V, a source voltage Vs of 0V, and a bit line voltage Vbl of 0V.
Particularly, a flash memory cell is programmed by increasing its threshold voltage while channel hot electrons generated by a big potential difference applied to the drain and source of the flash memory cell are moving to the floating gate. Upon such programming, a predetermined amount of operating current is consumed. The performance of flash memory depends on how much the operation current consumption is reduced. Also, when a flash memory cell is programmed, the bit line voltage Vbl must be applied to the drain of the flash memory cell in order to prevent its threshold voltage from being changed due to unintended stress, that is, punch through disturbing caused by unselected flash memory cells because of the structure of a flash memory cell array in which a plurality of flash memory cells share a bit line.
FIG. 4 is a schematic circuit diagram of a conventional program wordline voltage generation circuit. Referring to FIG. 4, a constant current generator 410 generates a program current Ipgm. A first PMOS transistor P1 transfers the program current Ipgm to a second PMOS transistor P2. Here, the first and second PMOS transistors P1 and P2 constitute a current mirror. The program current Ipgm flows along a path from the second PMOS transistor P2 to a resistor R via a cell capacitor C1. The cell transistor C1 is formed of a diode type in which a control gate and a drain are coupled to each other. A voltage for a connection node between the second PMOS transistor P2 and the cell transistor C is generated as a wordline voltage Vwl and provided to a core cell array.
FIG. 5 is a graph showing a distribution of the program wordline voltage Vwl generated by the conventional program wordline voltage generation circuit of FIG. 4. Referring to FIG. 5, the program wordline voltage Vwl is changed to first, second, and third program wordline voltages Vwl1, Vwl2, and Vwl3 as the program current Ipgm is changed to first, second, and third program currents Ipgm1, Ipgm2, and Ipgm3. That is, a variation in the program current Ipgm directly affects the generation of the program wordline voltage Vwl. The program current Ipgm varies with a change in a process of manufacturing a flash memory device, and the variation of the program current Ipgm changes the level of the wordline voltage Vwl of FIG. 4 desired upon programming. The variation of the program current Ipgm also changes the bitline voltage Vbl applied to both ends of the resistor R of the conventional program wordline voltage generation circuit of FIG. 4.
FIG. 6 is a schematic circuit diagram of a conventional circuit for controlling a bitline current that is applied to bitlines of a flash memory cell upon programming. Referring to FIG. 6, a constant current source 610 generates a program current Ipgm. A third PMOS transistor P3 transfers the program current Ipgm to a fourth PMOS transistor P4. Here, the third and fourth PMOS transistors P3 and P4 constitute a current mirror. The program current Ipgm flows along a path of from the fourth PMOS transistor P4 to an NMOS transistor N1 whose gate and drain are coupled to each other. Referring to FIG. 7, which is a graph showing the operation of the NMOS transistor N1, if the constant program current Ipgm flows along a path between the drain and source of the NMOS transistor N1, a voltage flowing between the gate and source of the NMOS transistor N1 is a bitline current control voltage Vgc.
The bitline current control voltage Vgc is applied to the gate of an NMOS transistor N2 coupled to a flash memory cell C2 of FIG. 8. The program wordline voltage Vwl and the bitline voltage Vbl are respectively applied to the gate and drain of the flash memory cell C2. While the program current Ipgm is flowing to the flash memory cell C2 provided with the aforementioned voltages, the flash memory cell C2 is programmed.
To program the flash memory cell C2, the wordline voltage generation circuit of FIG. 4 and the bitline current control circuit of FIG. 6 must be exactly aware of the current characteristics of the flash memory cell C2 in order to set an ideal program current Ipgm. If the program current Ipgm varies with a process change, the program wordline voltage Vwl, which causes the program current Ipgm to flow into the flash memory cell C2, also varies, which impedes generation of an accurate program current Ipgm to flow to the flash memory cell C2. Consequently, the flash memory cell C2 is unstably programmed.
Therefore, a flash memory device that can program flash memory cells by providing a program wordline voltage Vwl and a bitline current control voltage Vgc that are stable against a process change is required.